1. Field of the Invention
The present invention relates to, e.g., an NAND flash memory using an EEPROM, and more particularly to a semiconductor memory device capable of storing multivalued data in a single memory cell.
2. Description of the Related Art
In an NAND flash memory, a plurality of memory cells arranged in a column direction are connected in series to constitute NAND cells, and each NAND cell is connected with a corresponding bit line through a selection gate. Each bit line is connected with a latch circuit which latches write data and read data. All or a half of a plurality of cells arranged in a row direction are simultaneously selected, and a write or read operation is collectively carried out with respect to all or a half of the cells selected at the same time. The plurality of NAND cells arranged in the row direction constitute a block, and an erase operation is executed in this block unit. In the erase operation, a threshold voltage of the memory cells is set to a negative voltage. Injecting electrons into the memory cells in a write operation can set the threshold voltage to a positive voltage (see, e.g., Jpn. Pat. Appln. Publication No. 2004-192789).
Meanwhile, in the NAND cell, the memory cells are connected in series. Therefore, in a read operation, a non-selected cell must be in an on state, a voltage (Vread) higher than a threshold voltage is applied to a gate electrode of the non-selected cell. Therefore, in the write operation, the threshold voltage set with respect to cells must not exceed Vread, and a threshold distribution is controlled in such a manner that it does not exceed Vread by repeatedly executing a program operation and a program verify read operation in accordance with each bit in a write sequence.
Further, in recent years, with an increase in a capacity of a memory, a multivalued memory which stores two or more bits in one cell has been developed. For example, in order to store two bits in one cell, four threshold distributions must be set in such a manner that each distribution does not exceed Vread. Therefore, each threshold distribution must be controlled to be narrowed as compared with a case where one bit or two threshold distributions are stored in one cell. Furthermore, in order to store three bits or four bits in one cell, eight or 16 threshold distributions must be set. Therefore, a distribution width of each threshold voltage must be greatly narrowed. In order to narrow a distribution width of a threshold voltage in this manner, a program and a verify operation must be precisely repeated, and there occurs a problem of a decrease in a writing speed. Therefore, a semiconductor memory device capable of increasing a writing speed has been demanded.